Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or metal oxide semiconductor (MOS) transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel and that is separated from the channel by a gate dielectric structure. The ICs are usually formed using both P-channel FETs (PMOS transistors or PFETs) and N-channel FETs (NMOS transistors or NFETs) and the IC is then referred to as a complementary MOS or CMOS circuit. Some semiconductor ICs, such as high-performance microprocessors, can include millions of FETs.
In addition to FETs, ICs also generally include additional functional devices such as memory devices. Flash memory devices, in particular, generally include a floating gate structure formed over a P-channel or an N-channel, with a control gate formed over the floating gate and with a dielectric layer separating the floating gate from both an underlying semiconductor substrate and from the control gate. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. As advanced metal-oxide-semiconductor (MOS) technology continues to scale and move into the deep-sub-micron geometry dimensions, advancements to techniques for further decreasing critical dimension (CD) of features have been sought. Especially for so-called planar IC architectures, wherein transistors and memory devices are formed layer-by-layer over and on a semiconductor substrate, efforts to decrease critical dimensions often involve decreasing cross-sectional area of the gate structures as well as decreasing gap spacing between the gate structures. However, as spacing decreases between gate structures, aspect ratios between gate height and gap width between gate structures increase. The increase in aspect ratios between the gate height and gap width between gate structures renders gap fill with dielectric material more difficult, often leading to void formation in an interlayer dielectric layer formed from the dielectric material in the area of the gap between the gate structures. The prevalence of such void formation is of particular concern for gate structures that include multiple distinct gates that are vertically formed over the semiconductor substrate, such as the gate structures in the flash memory devices, due to generally high aspect ratios between the gate height and the gap width between gate structures.
Accordingly, it is desirable to provide methods of forming integrated circuits that address interlayer dielectric void formation between gate structures. In addition, it is desirable to provide methods of forming integrated circuits that are effective to address such void formation without materially impacting sensitive structures that underlie the interlayer dielectric layer that is formed over and between the gate structures. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.